Dr. L. Swarna jyothi

photo Dr. L. Swarna jyothi

Faculty Details

Faculty Name

Dr. L. Swarna jyothi

Brief Profile

Studied B.E Degree in Electronics and communication in BMS College of Engg, Bangalore under Bangalore University, M.E from Anna University, Chennai and PhD from Dr MGR research and Education University. Has just finished working for a startup company as a Director. She has worked as an advisor. The company has developed technologies to alleviate gender based violence.Has worked earlier as the principal at Jnanavikas Institute of Technology and brought in many improvements in overall discipline,teaching learning and skill development. Instrumental in using open and free softwares in all labs and teaching the students as per university requirements. Has associated with VTU and Bangalore university as part of BOE ,evaluation process and syllabus formulation etc.
Has taught in JSS Academy of Technical Education, Bangalore for over 8 years and worked as professor and Head. She has been campus coordinator for industry-Institution interaction programs for excellent projects under open source category, induction programs etc with Wipro, cognizant, Sun Micro Systems etc. Instrumental in getting NBA Accreditation to the department. Has also completed research project as the principal Investigator for AICTE-RPS project. Has worked in BMS College of Engg, Bangalore for over 21 years in various capacities with an humble start as a lecturer. She has played various roles such as Head of the Department, PG coordinator, Placement officer, ISTE faculty coordinator, Faculty advisor technical-Melton foundation and coordinator three AICTE projects.

Research and Projects

Application specific circuit FPGA/ASIC front end design, Design reuse, verification Reuse. She has around 20 papers to her credit published national/International conferences/Journals with Technical partnership such as IEEE, Springer etc. She been the coordinator for three AICTE projects for developing and using the infrastructure for FPGA and ASIC based designs and development at BMS College of Engg. She has also completed a AICTE-RPS research project for design for verification of Reusable Verification Environment.


H.O.D & Professor


Electronics and Communication Engineering

Date of Birth



B.E, M.E, Ph.D

Date of Joining



FPGA/ASIC front end design, Design reuse, verification Reuse


35 Years